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Subject: comp.lsi.cad Frequently Asked Questions With Answers (Part 3/4) [LONG]

This article was archived around: 10 Jan 1997 00:53:31 GMT

All FAQs in Directory: lsi-cad-faq
All FAQs posted in: comp.lsi, comp.lsi.cad
Source: Usenet Version

Archive-name: lsi-cad-faq/part3 Posting-Freqency: every 14 days URL: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html
- 1 schematic page (unlimited hierarchy) - up to 25 parts on a page - A-size page only - up to 20 user-defined symbols - no printing from within the Symbol Editor - no export/import of symbols - number of Symbol Library files that can be loaded is limited to the total number shipped plus one Netlister limitations include: - up to 70 real devices for PSpice A/D netlists - up to 50 symbols, before packaging, for PCB layout netlists The following files are needed (use password 'anonymous': <URL:ftp://ftp.netcom.com/pub/mi/microsim/62wine.exe> <URL:ftp://ftp.netcom.com/pub/mi/microsim/62plsyne.exe> <URL:ftp://ftp.netcom.com/pub/mi/microsim/readme.txt> <URL:ftp://ftp.netcom.com/pub/mi/microsim/train.txt> <URL:ftp://ftp.netcom.com/pub/mi/microsim/tutor.exe> <URL:ftp://ftp.netcom.com/pub/mi/microsim/win32s25.exe> A version for windows is also available. Read <URL:ftp://ftp.netcom.com/pub/mi/microsim/.message> to determine the necessary files. 31: Esim: A new version of the switch-level simulator ESIM that can handle CMOS transmission gates is available through MUG, ftp ftp.mosis.edu ( 32: iSPLICE3, a mixed-mode simulator for MOS/Bipolar circuits (from Xiaocun Xu <xu@uivlsi.csl.uiuc.edu>) "iSPLICE3: A Mixed-Mode Simulator for MOS/Bipolar Circuits" The iSPLICE3 program is the third version of the SPLICE mixed-mode simu- lation program currently under development at the University of Illinois, based on research work originally initiated at the University of Califor- nia at Berkeley. A mixed-mode simulator allows the circuit designer to intelligently tradeoff simulation accuracy for speed within the scope of a single simulator. The circuit designer is permitted to represent dif- ferent parts of the same circuit at different levels of abstraction and the mixed-mode simulator combines the different representations, models and signal types in one simulation and produces the desired results while greatly reducing the overall run-time. Currently, the iSPLICE3 program has electrical, logic and and switch-level timing simulation modes. The electrical analysis is performed using Iterated Timing Analysis (ITA) which is an accurate, event-driven, relaxation-based circuit simulation technique. The transistor models include MOS level 1, MOS level 3, the TI MOS model due to Yang and Chatterjee and a Bipolar transistor model from SPICE2. Accurate switch-level simulation is performed using ELOGIC. In this mode, a set of discrete voltage states are defined and the time required to make a transition between two adjacent states is computed using electrical information. The precision of the model can be adjusted to suit the desired level of accuracy. For logic simulation, simple gates such as inverters, nors, nands, etc. are available with fanout- dependent delay models. The program can be obtained from the University of Illinois by writing to: Prof. R. Saleh, RE: Splice Program Coordinated Science Laboratory University of Illinois, Urbana, IL. 61801. There is a $100 cost for the tape, documentation, userguide and handling charges for university or academic requests. FTP access is free of charge on uivlsi.csl.uiuc.edu. There is a $400 charge to companies for the entire tape/documentation set but no charge for FTP access. Please make checks payable to the University of Illinois. Please request either a Sun-tape or a 1600bpi magnetic tape. 33: Watand: (From Phil Munro <FC138001@ysub.ysu.edu>) This posting will give the interested person some information about the WATAND (WATerloo ANalysis and Design) circuit simulator. Watand was introduced at the 16th Midwest Symposium on Circuit Theory (1973). In spite of its lack of advertising, Watand still offers some advantages when compared with other well known circuit simulators. For example it is a *truly* interactive simulator; that is, one enters the "WATAND" environment in which analyses and design can be run and rerun, values changed, settings queried and changed, etc. Watand uses piecewise-linear as its primary simulation; other methods are optional. It has ten built-in analyses which include the standard dc, ac, and transient analyses, and two post-processors (display and discrete Fourier). Output may be in the form of printed tables; graphics display includes Tektronix 40xx output. At YSU interactive helps are also available. Watand provides for the creation and use of user defined elements in addition to its own good stock of 34 built-in elements plus 21 built-in user defined elements. User defined analyses and post-processors can also be written, and it includes a powerful macro facility. As of June, 1992, sale of the Watand simulator was still being handled by Mark O'Leavey, Waterloo Engineering Software, 22 King St. S., Suite 302, Waterloo, Ontario, CANADA, N2L 1C6, Fax: (519) 746-7931; Phone: (519) 741-8097. At that time I was informed that it was available only for DECStation and Sparcstation, although we are running it quite suc- cessfully at YSU under the CMS operation system on an Amdahl mainframe. Two new and helpful manuals are available for the simulator. They should be available at the Youngstown State University Bookstore, Youngs- town, OHio 44555: Their approximate cost should be $7 each: "WATAND Users Manual," by Dr. Phil Munro, Youngstown State University, April 1992, 233 pages, 10 chapters, 4 appendices, index. "WATAND Introduction and Examples," by Dr. Phil Munro, Youngstown State Unversity, June 1992, 204 pages, 12 chapters, index. Watand does *not* include digital simulation at this time, nor does it have any transmission-line elements. A self-heating BJT model has been developed and is proving useful. Monte Carlo statistical simulation is possible with dc and ac analyses using macro based analyses which have been developed at YSU. 34: Caltech VLSI CAD Tools: (From John Lazzaro <lazzaro@cs.berkeley.edu>) Caltech VLSI CAD Tool Distribution - The Chipmunk Tools The software tools in the Chipmunk system perform a wide variety of tasks: electronic circuit simulation and schematic capture, graphics editing, and curve plotting, to name a few. The tools run under a wide assortment of Unix environments, as well as OS/2. Major Chipmunk tools include: Log: A graphical environment for entering circuit schematics, and for analog and digital circuit simulation. View: A tool for manipulating and plotting data. Until: A graphics editor. Wol: A tool for creating integrated circuit layout. In addition to these major tools, many smaller tools are part of the Chipmunk system. For more information on Chipmunk, access the Web page: http://www.pcmp.caltech.edu/chipmunk/ or anonymous FTP to pcmp.caltech.edu and get the file: pub/chipmunk/README Contact the maintainer, John Lazzaro (lazzaro@cs.berkeley.edu) if you have problems accessing the distribution. 35: Switcap2 (Current version 1.1): This is a switched capactor simulator. It is available from: SWITCAP Distribution centre, 411 Low Memorial Library, New York, N.Y. 10027. 36: Test Software based on Abramovici Text: (Contributed by Mel Breuer of the Univ. of Southern California) Many faculty are using the text by Abramovici, Breuer, and Fried- man entitled "Digital Systems Testing and Testable Design" in a class on testing. They have expressed an interest to supplement their course with software tools. At USC we have developed such a suite of tools. They include a good value simulator, fault simulator, fault col- lapsing module, and D-algorithm-based ATPG module for combinational logic. The software has been specifi- cally designed to be easily understood, modified and enhanced. The algorithms follow those described in the text. The software can be run in many modes, such as one module at a time, single step, interactively or as a batch process. Stu- dents can use the software "as is" to study the operation of the various algo- rithms, e.g. simulation of a latch using different delay models. Also, simple programming projects can be given, such as extend the simulator from a 3-valued system to a 5-valued system; or change the D-algorithm so that it only does single path sensiti- zation. There are literally over 50 interesting software enhancements that can be made by changing only a small part of the code. The system is written in C and runs on a SUN. If you are currently using the Abramovici text and would like a copy of this software, please send a message to Prof. Melvin Breuer at mb@poisson.usc.edu. 37: Test Generation and Fault Simulation Software (Contributed by Dr. Dong Ha of Virginia Tech) Two automatic test pattern generators (ATPGs) and a fault simula- tor for combinational circuits were developed at Virginia Tech, and the source codes of the tools are now ready for public release. ATLANTA is an ATPG for stuck-at faults. It is based on the FAN algorithm and a parallel-pattern, single-fault propaga- tion technique. It consists of optional sessions using random pattern testing, deterministic test pattern generation and test compaction. SOPRANO is an ATPG for stuck-open faults. The algo- rithm of SOPRANO is similar to ATLANTA except two consecutive patterns are applied to detect a stuck-open fault. FSIM is a parallel-pattern, single-fault simulator. All the tools are written in C. The source codes are fully commented, and README files contain user's manuals. Technical papers about the tools were presented at DAC-90 and ITC-91. All three tools are free to univer- sities. Companies are requested to make a contribution of $5000 but will have free technical assistance. For detailed in- formation, con- tact: Dr. Dong Ha Electrical Engineering Virginia Tech Blacksburg, VA 24061 TEL: 703-231-4942 FAX: 703-231-3362 dsha@vtvm1.cc.vt.edu 38: Olympus Synthesis System (From Rajesh K. Gupta <rgupta@sirius.Stanford.EDU>) Recently there have been several enquiries about the Olympus Synthesis System. Here are answers to some commonly asked questions. For details please send mail to "synthesis@chronos.stanford.edu". 1. What is Olympus Synthesis System? Olympus is a result of a continuing project on synthesis of digital cir- cuits here at Stanford University. Currently, Olympus synthesis system consists of a set of programs that perform synthesis tasks for synchro- nous, non-pipelined circuits starting from a description in a hardware description language, HardwareC. The output of synthesis is a technology independent netlist of gates. This netlist can be input to logic synthesis and technology mapping tools within Olympus or to UC Berkeley's mis/sis. Current technology mapping in Olympus is targeted for LSI logic standard cells and a set of PGA archi- tectures: Actel and Xilinx. 2. How is Olympus distributed? The source code and documentation for Olympus is distributed via ftp. 3. What are the system requirements for Olympus? Olympus has been tested on following hardware platforms: mips, sparc, hp9000s300, hp9000s800, hp9000s700, vax. All the programs in Olympus come with a default menu-driven ASCII interface. There is also a graphi- cal user interface, called "olympus", provided with the distribution. This interface is written using Motif procedures. You would need about 40 MBytes of disk space to extract and compile the system. 4. How can I obtain a copy of Olympus? Olympus is distributed free of charge by Stanford University. However, it is not available via anonymous ftp. In order to obtain a copy please send a mail to "olympus@chronos.stanford.edu" where an automatic-reply mailer would send instructions for obtaining Olympus software. 39: OASIS logic synthesis (From William R. Richards Jr. <richards@mcnc.org>) OASIS is a complete logic synthesis system based on the Logic3 HDL develped at MCNC (unfortunately neither VHDL or Verilog compatible). kk@mcnc.org is the person responsible for it. OASIS is available to US universities for $500 and non-US universities for $600. Industrial license is $3000. 40: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator (From William R. Richards Jr. <richards@mcnc.org>) CAzM is a Spice-like table-based analog circuit simulator. It offers sig- nificant performance advantages over other Berkeley Spice derivatives. It is used fairly extensively in our design community. US university license is $175, non-US $250. Commercial license is $800. It comes with an X11- based signal viewing tool Sigview which is public domain and may be anonymous ftp'd from mcnc.org. I am the primary contact for CAzM at MCNC. (Contact sales@tanner.com) The CAzM program that was developed and offered by MCNC, has been licensed for distribution by Tanner Research, Inc. of Pasadena, CA and all future product availability and support is available from Tanner Research. The program as offered by Tanner Research is a commercial pro- duct and is now named T-Spice. This Spice-like simulator offers table- based model evaluations for fast simulation performance, as well as, included analytical models for use with digital and analog circuits. Improvements to the CAzM models have also been made. Tanner Research offers an optional Advance Model Library of charged controlled models that includes an accurate, physically-based MOSFET model that is continu- ous over all transistor regions of operations (including subthreshold), and scales to submicron channel lengths. User defined models of any cus- tom component or circuit written in "C" can be readily linked to T-Spice as a general n-terminal device. Pricing is $995 for the simulator and $1,245 with the Advance Model Library and Waveform Viewer. Universities are offered a 75% discount. A modeling and extraction service is also provided by Tanner Research to generate functional or transistor level circuit simulation models for user supplied devices. The extraction ser- vice provides extracted model parameters for existing circuit simulation models, such as SPICE models, Tanner's own charge controlled MOS models, or user's proprietary models. In addition, software is available to aid users in extracting model parameters in house. For more information con- tact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone 818-792-3000 and fax 818-792-0300. 41: Galaxy CAD, integrated environment for digital design for Macintosh Thanks to Simon Leung <sleung@sun1.atitech.ca> The Galaxy CAD System is an integrated environment for digital design and for rapid prototyping of CAD tools and other software. The system currently includes schematic capture and simulation of both low-level and high-level digital designs and is being expanded to include physical design tools. Galaxy runs on a number of 680X0 platforms, including the Apple Macintosh, HP9000/3XX, Apollo Domain, and Atari ST. Others will be added according to demand. The Galaxy CAD System is an ideal environment for teaching digital design. It has been used successfully for both introductory logic design and computer design courses at Wisconsin. Some of the features of Galaxy that make it suitable for education are: 1. Integrated multiple-window environment: All Galaxy tools run concurrently in a multiple window environment. Copying data from one window to another is simple. Any number of simulation sessions can be active simultaneously. 2. Hierarchy: the schematic editor and simulator are both fully hierarchical. Building hierarchical designs is simple, including creating symbols for modules. The simulator is a true hierarchical simulator: it does not require a time-consuming macro-expansion step. 3. Integrated editing and simulation: Designs are edited and simulated in the same environment. Simulation input and output can be shown directly on schematics, allowing direct manipulation of net values. Unlike other products, Galaxy does not require modification of the schematic to insert "switch" and "light" components. In addition, Galaxy allows display of bus values in hexadecimal directly on schematics to simplify debugging of high-level designs. Simulation I/O can also use waveforms, text files, and tables. 4. Faults: Stuck-at faults can be introduced on the schematic editor and simulated immediately without rebuilding the simulation model. This provides an excellent way to display the effects of faults. 5. Buses: Galaxy supports specification and simulation of bus structures, including complex extractions, fanouts, and bit reversal. Buses are specified by annotating nets with text. For simulation, buses are kept intact so that multiple-bit high-level components can be used. Galaxy includes a library of register-transfer components suitable for high-level computer design and simulation. 6. Alternate specification of designs: In addition to schematics, Galaxy users can specify design modules using a textual HDL (GHDL) and using hardware flowcharts and state diagrams. A hierarchical design can mix these representations as desired. 7. High-quality PostScript output: Galaxy schematics are of excellent quality. Gates are drawn according to standard practices, e.g., OR gates are drawn with the correct circular arcs and not ellipses. 8. Uniform user interface: Galaxy tools have the same user interface on all platforms, reducing student learning curves. In fact, the same tool OBJECT CODE runs on all platforms due to the unique structure of Galaxy. 9. Adding new simulation primitives is straightforward. 10. No cost: Galaxy is available for free via anonymous FTP (Apple Macintosh version). Other versions will be made available based on demand. Galaxy is also an excellent environment for rapid prototyping of new CAD tools. By building on top of available resources, we have been able to prototype new tools in days or weeks that would ordinarily have taken months or years. For more information, send e-mail. To obtain Galaxy CAD, connect to "ftp://eceserv0.ece.wisc.edu/pub/galaxy" using FTP. Log in as "anonymous" with password "guest". Galaxy is in directory "pub/galaxy". The file "README" in that directory gives further instructions. Please register as a user by sending e-mail to "beetem@engr.wisc.edu". John F. Beetem ECE Department University of Wisconsin - Madison Madison, WI 53706 USA (608) 262-6229 beetem@engr.wisc.edu 42: WireC graphical/procedural system for schematic information (From Larry McMurchie <larry@cs.washington.edu>) WireC is a graphical specification language that combines schematics with procedural constructs for describing complex microelectronic systems. WireC allows the designer to choose the appropriate representation, either graphical or procedural, at a fine-grain level depending on the characteristics of the circuit being designed. Drawing traditional schematic symbols and their interconnections provides fast intuitive interaction with a circuit design while procedural constructs give the power and flexibility to describe circuit structures algorithmically and allow single descriptions to represent whole families of devices. The procedural capability of WireC allows other CAD tools to be incor- porated into the design system. For example, we have defined an inter- face to the SIS logic synthesis system wherein the designer can represent part of the system behaviorally. WireC invokes logic synthesis on these components to produce a structural description that can be incorporated into the rest of the design. Libraries of devices defining a particular netlist output format may be defined by the user. The libraries currently distributed with WireC include a default CMOS gate library whose output is the SIM format. This format can be simulated with COSMOS or IRSIM and compared against a cir- cuit extracted from layout. This library also includes devices that allow a behavioral description to be synthesized and mapped using MIS or SIS and incorporated into a larger circuit. Another library is the xnf library for designing systems with Xilinx FPGAs. Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC, this library contains devices specific to the 2000 and 3000 series Xilinx LCA's. In addition to drawing the devices explicitly, one can represent parts of a circuit with equations and have these synthesized automati- cally. Currently in progress is a library of CMOS gates for Cascade Design Automation's ChipCrafter product. WireC provides a mixed schematic/procedural design frontend for ChipCrafter, which uses module generation, timing analysis and place and route software to create a phy- sical layout from the WireC design specification. WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed Tellman. We are interested in any libraries you may develop and will provide a limited degree of support. WireC requires an X-Windows compatible environment and a C++ compiler such as Gnu G++ and AT&T CC. WireC is available via ftp on the Internet. For details send mail to larry@cs.washington.edu ebeling@cs.washington.edu 43: LateX circuit symbols for schematic generation (From Adrian Johnstone <adrian@cs.rhbnc.ac.uk>) A set of circuit schematic symbols are available for use in LaTeX picture mode. The set includes all basic logic gates in four orientations, FETs, power supply pins, transmission gates, capacitors, resistors and wiring T-junctions. All pins are on a 1mm grid and the symbols are designed to be easily used with Georg Horn's TeXcad program: we even supply you with a palette picture file that displays all 52 symbols in a compact grid that you can cut and paste from within TeXcad. Each symbol lives in its own .mac file and is defined as a 'savebox' so as to reduce memory con- sumption. You must add the [bezier] option to your 'documentstyle' com- mand. A small manual is provided in both Postscript and .dvi forms. The files lcircuit.zip and lcircuit.tar are available for anonymous ftp from ftp://cscx.cs.rhbnc.ac.uk/pub/lcircuit ( I will also be uploading them to various ftp servers in the coming week. 44: Tanner Research Tools (Ledit and LVS) (Contact sales@tanner.com) Low cost, yet very powerful commercial ASIC design tools are available from Tanner Research, Inc. in Pasadena, CA. These products are used by industry and universities alike. Tanner's products are nominally priced at $995 per program, with a combined package named L-Edit Pro available for $3,495 on the PC. Universities are offered a 75% discount. Here is a list of their current programs: L-EditTM : A full-custom layout editor with CIF and GDSII input/output. Features a 32-bit coordinate space, all-angle geometry, unlimited hierarchy and number of layers. The L-Edit Pro package includes L-Edit/DRC for design rule checking, L-Edit/SPR for automatic standard cell placement and routing, L-Edit/Extract for extracting transistors, capacitors, resistors and generic devices for SPICE-level simulation or comparison to a schematic and LVS ,a netlist comparison tool for topological and parametrical verification. Optional layout libraries are also available. T-Spice: Circuit level simulator (See item 41 for detail GateSimTM : Gate-level simulator. A full array of technology mapping libraries are also available. Products are available for the PC, Macintosh, Sun and Hp UNIX platforms. For more information contact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone 818-792-3000 and fax 818-792-0300. 45: SIMIC, a full-featured logic verification simulator. (From comp.archives.msdos.announce) SIMIC is a full-featured logic verification simulator. It has been demonstrated that SIMIC can uncover a number of critical design errors that other simulators miss. SIMIC has shown superior accuracy and throughput when compared to competitive products. Here are some of SIMIC's important features: - Mixed-mode simulation allows the free intermixture of true bilateral switches (ideal and resistive), gate, plus functional level built-in and user defined primitives. - A wide variety of output, whose detail, content and format are, to large extent, user defined. - A large repetoire of simulation options and controls that can be applied interactively, or in batch operation, and simplify trouble-shooting of your design. - Automated Test equipment emulation, allows debugging test programs using SIMIC troubleshooting techniques. - Sophisticated hazard analysis including: Spike, Pulse, Conflict, Oscillation, Setup, Hold, Pulse-width, Near (what-if) detection, among others. Hazard propagation is also supported. The student version of SIMIC is limited to a maximum of 500 elements (parts). In all other respects it is the same program as the commercial offering. The PC student version requires a 386 or better and at least 2 Meg of memory. Both a DPMI and a VCPI version are included in the pack- age. Both versions require EMS *NOT* be disabled. SIMIC is also avail- able on Sun and other platforms. The latest version is 1.02.00. The changes from revision 1.00.04 are: Bug Fixes: - Rams properly handled by circuit compiler. - BTG (Ideal switches) compiled correctly with dynamic delays. - By-name pin connections accepted by circuit compiler. - JK Flip-flop timing checks can now be disabled. Enhancements: - Reduction in storage requirements for small RAMS. - Fault Sensitization analysis added. - Fault Simulation and grading added. This revision can be taken from ftp://oak.oakland.edu/pub/msdos/electric, or ftp://wuarchive.wustl.edu/systems/msdos/electric . The files in ques- tion are sim120bn.zip (Simic logic and fault simulator plus examples) and sim120dc.zip (Simic Engineering and User's Guides). The latest version is: <URL:ftp://ftp.njcc.com/pub/genashor/simoc/msdos/simic.zip> 46: LASI CAD System, IC and device layout for IBM compatibles (from Mike Fitsimmons <mikef@eceuil.ece.uiuc.edu>) I have uploaded to SimTel, the Coast to Coast Software Repository (tm), (available by anonymous ftp from the primary mirror site OAK.Oakland.Edu and its mirrors): SimTel/msdos/cad/ lasi442a.zip LASI v4.4.2 IC layout CAD pgm; unzip in lasi442b.zip LASI v4.4.2 IC layout CAD pgm; unzip in lasi442c.zip LASI v4.4.2 IC layout CAD pgm; unzip in This is Version 4.4.2 of the LASI CAD System that has been released expressly for Internet by Dr. Dave Boyce the author. LASI was developed to do integrated circuit and device layout on almost any IBM compatible personal computer. It may be used for other CAD applications such as schematics or printed circuit boards. Drawings may be translated into GDSII, CIF or HP-GL. It is a CAD system that is easy to learn and run, and is primarily intended for educational use in schools and colleges by students, researchers, or anyone who doesn't have time of funding for more elaborate CAD systems. Changes: This version contains many improvements to LASI itself, the HP- GL plotter, the CIF converter and other programs. The condensed files are in three zipped files LASI442A.ZIP, LASI442B.ZIP and LASI442C.ZIP. You must have all three zipped files to have a complete set of LASI files. Uploaded on behalf of the author. 47: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles This is available from SimTel mirror sites such as: <ftp://oak.oakland.edu/SimTel/msdos/graphics/eedraw24.zip> This is the 2.4 release of EEDRAW, an electrical/electronic diagramming tool for the IBM PC. Electrical Engineering drawing (with layers). Please read the readme file in the primary archive for information on other source programs needed such as the Libary files. 48: MagiCAD, GaAs Gate Array Design through MOSIS (from Tom Smit <smith.thomas@mayo.edu>) MagiCAD is a system for GaAs semi-custom design through MOSIS and elec- tromagnetic modeling of digital interconnect. MagiCAD is now available on the following platforms: * DEC Alpha workstation running OSF/1 2.0 * HP 9000/700-series workstation running HP-UX 9.05 * Sun SparcStation running Solaris 2.3 (SunOS 5.3) The Mayo Graphical Integrated Computer Aided Design (MagiCAD) system package provides a comprehensive design environment for the development of digital systems, from initial concept to post-layout verification of integrated circuits (ICs). MagiCAD focuses on the development of high- speed Gallium Arsenide (GaAs) gate array designs. Specialized elec- tromagnetic simulation tools are provided to address high clock rate issues such as crosstalk and reflections, which become more important as clock rates exceed several hundred MHz or signal edge rates become less than 500 pico-seconds. MagiCAD provides all the necessary tools for high clock rate GaAs IC design, and is also integrated with non-Mayo circuit, logic, and fault simulators. MagiCAD provides a lower risk approach than full-custom design for universities wishing to perform digital GaAs design through MOSIS. This is done by providing a gate array design environment where low-level transistor design and layout issues have already been solved and abstracted into a technology library of pre-defined cells. This frees the student or researcher to solve the still challenging tasks of system and gate-level design and layout to get high clock rate chips fabricated through MOSIS that meet all specifications. MagiCAD has been used in the design of many GaAs chips that have been successfully fabricated. The MagiCAD electromagnetic modeling tools have been used in the analysis of many actual packages, multi-chip modules (MCMs), and printed circuit boards (PCBs), uncovering and avoiding prob- lems that are commonly associated with high-frequency, fast edge-rate designs. The Vitesse Fury (TM) GaAs VSC2K gate array is provided as a MagiCAD technology library, and has been used for both graduate and undergraduate student chip designs. The Vitesse FX20K (HGaAs-III) has been entered as a MagiCAD technology library, as a replacement for the VSC2K (HGaAs-II). A Mayo FX20K chip design is in fabrication now, and after it is tested, the FX20K technology will be released for student designs through MOSIS by 2Q 1995. Functionality that has been integrated into MagiCAD includes: o Vitesse Fury VSC2K GaAs gate array technology library (HGaAs-II) o Database which integrates all tools o Schematic entry through a general purpose graphics editor o Circuit simulator o Logic and timing simulators o Fault grading o Place and route tools o Layout verification tools o Output to standard GDSII format for mask creation o Electromagnetic analysis - Cross section entry with graphics editor - Multilayer multiconductor transmission line (MMTL) modeling - Network tool for solving cases with many transmission line components - Lossy and non-lossy cases - Frequency and time domain result displays - Used for analyzing complex design paths, through chip, MCM, and PCB The Advanced Research Projects Agency (ARPA) has funded Mayo to supply MagiCAD to universities in the USA for research and educational purposes. The direct cost to the universities for the MagiCAD software itself is zero (although there may be costs for any non-Mayo software that univer- sities may want). Mayo-supplied MagiCAD training and support costs to these institutions is funded by ARPA, and is therefore free to the universities in the USA. MagiCAD is not being distributed or supported outside the USA. The general steps for a university to begin using MagiCAD for digital GaAs gate array design include: 1) Contact Mayo Foundation to acquire MagiCAD software and GaAs technology libraries. 2) Contact MOSIS to acquire general MOSIS information and Vitesse-specific GaAs technology information. Point Of Contact For Acquiring MagiCAD And MagiCAD Support: Tom Smith Mayo Foundation Special Purpose Processor Development Group 200 First St. S. W., Guggenheim 1016A Rochester, Minnesota 55905 Telephone: (507) 284-0840 Telefax: (507) 284-9171 EMail: Smith.Thomas@Mayo.Edu Point Of Contact For Acquiring General MOSIS Information And Vitesse- specific GaAs Technology Information: Sam Reynolds The MOSIS Service USC/ISI 4676 Admiralty Way Marina del Rey, CA 90292-6695 Telephone: (310) 822-1511 x172 Telefax: (310) 823-5624 EMail: sdreynolds@mosis.edu 49: XSPICE, extended version of Spice (from Jeff Murray <jm67@hydra.gatech.edu>) I am one of the developers of XSPICE, and at the risk of being deluged with requests for specific information on the tools, I can volunteer to answer at least some questions. Currently there is no ftp site for infor- mation; if there were, this posting would likely be unnecessary. However, we are prohibited from posting even the User's Manual due to technology export restrictions. The following is a copy of the original press release on XSPICE. If anyone would like additional clarification beyond this, or if some aspects of the release are unclear, we can certainly take this as an opportunity to remedy the situation. Please note that at the current time there are many dozens of individuals who have obtained a copy of the tools; if they have any comments or observations to make, I'm sure they would be most welcome to other members of the user community. XSPICE Press Release January 2, 1993 Georgia Tech Research Corporation XSPICE, introduced at the 1992 International Symposium on Circuits and Systems (ISCAS), is an extended and enhanced version of the popular SPICE analog circuit simulation program originally developed at the University of California at Berkeley. XSPICE was developed at the Georgia Tech Research Institute (GTRI) as a tool for simulating circuits and systems at multiple levels of abstraction. XSPICE permits a user to simulate ana- log, digital, and even non-electronic designs from the circuit level through the system level in a single simulator. A special Code Modeling feature allows users to add new models directly into the simulator exe- cutable for maximum simulation speed and accuracy. Code models are writ- ten in the C programming language allowing arbitrarily complex behavior to be described. Code model development tools are provided to simplify the process of creating new models, compiling them, and linking them with the XSPICE core. XSPICE provides a rich set of predefined code models in addition to the standard discrete device models available in SPICE. The XSPICE code model library contains over 40 new functional blocks including summers, multi- pliers, integrators, magnetics models, limiters, S-domain transfer func- tions, digital gates, digital storage elements, and a generalized digital state-machine. Digital functions are simulated in XSPICE through an embedded event- driven algorithm added to the SPICE core. This algorithm is coordinated with the analog simulation algorithm to provide fast and accurate simula- tion of mixed-signal circuits and systems. The event-driven algorithm supports a new "User-Defined Node" capability allowing additional event- driven data types to be defined and used. XSPICE comes with a 12-state digital data type as well as a user-defined node library that includes 'real' and 'integer' types useful in simulating sampled-data systems such as Digital Signal Processing algorithms. XSPICE is currently available for UNIX workstations and is supplied in source code form allowing users to customize and extend the simulator and models to particular needs. To date, the simulator has been successfully compiled and used on HP Apollo and Sun workstations. The XSPICE simulator and User's Manual are available with a cost-free license arrangement from the Georgia Tech Research Corporation for a distribution charge of US $200 (including first class postage within the U.S.A.; an additional US $25 is required for overseas delivery by air). For further information, please contact the Office of Technology Licensing, Georgia Tech Research Corporation, Georgia Institute of Technology, 400 Tenth Street, Atlanta, GA 30332-0415, USA, or phone (404) 894-6287 (voice) or (404) 894-9728 (FAX). Internet users may send email to XSPICE@GTRI.GATECH.EDU to obtain copies of the order form and license agreement (please include the word "license" in the subject header when mailing to this address). 50: MISIM, a model-independent circuit simulation tool (from Bardo Muller <bardo@ief-paris-sud.fr>) University of Washington has recently released the updated MISIM simula- tor. The new release (Sun version) is now available through ftp with anonymous login. The node address is The release is under /pub/misim.SUN.2.3.a. If you have any question, please don't hesitate to contact us (misim_support@ee.washington.edu). Or, you can contact Prof. Andrew Yang at 206-543-2932. Attention: --------- We are currently re-writing the whole MISIM system in C with broader design consideration. The noise and temperature simulation capability will be incorporated into our next release. It would have more flexible front end with better simulation performance. The new version is expected sometime around the end of this summer. Since the actual release no longer reflected the level of our technology, we removed it from our ftp directory. MISIM Development Team Department of Electrical Engineering University of Washington MISIM 2.3A Release: General Information ------------------------------------------ A) New capabilities: ---------------- MISIM 2.3A is distinguishable from the previous release in that is now integrates a transistor-level mixed analog-digital simulator based on analytical digital macromodeling. The mixed-signal simulator is equipped with a front-end translator which accepts standard SPICE netlist syntax and converts it into MISIM mixed-mode syntax. Analytic macromodels for digital subcircuits are generated and loaded into MISIM core simulator automatically. Synchronized simulation is then performed for the digital subcircuits (processed by analytic solution) and the analog subcircuits (processed by proven analog simulation algorithms) with much accelerated speed and superior analog accuracy ( within 3-5 % of SPICE). The MISIM mixed-signal simulator supports all standard Berkeley MOS model (Level 1, 2, 3, BSIM 1, BSIM 2). User-defined MOS models of arbitrary complexity are also supported. Currently, the procedure of processing analytic digital macromodeling cannot be applied to bipolar devices (G-P model). Hence, all bipolar transistors will be simulated as "analog" components. MISIM's X-window graphic environment, WISE, has been upgraded to support the mixed-signal simulation capabilities. B) Model Improvements: ------------------ MISIM 2.3A now supports improved SPICE models (MOS, Diode, BJT). Many of the model discontinuities have been resolved leading to more reliable simulation. The MOS Level 2 and Level 3 models have also been upgraded to an improved charge-conserved models. The standard SPICE diode model has been enhanced to a non-quasi-static model capable of simulating accu- rately the diode recovery effect. These improved SPICE models are released as linked models. Users are not recommeded to unload these improved models. C) A New Parser: ------------ MISIM 2.3A incorporates a new netlist parser which supports two different modes: 1) Standard SPICE netlist syntax - default mode. 2) Enhanced SPICE net- list syntax - MISIM mode. This new capability is designed to make MISIM completely spice- compatible. In addition, the new parser now handles symbolic names and expressions. D) Updated Documentations: ---------------------- An updated MISIM User's guide is available in postcript form. On-line documentations is also provided. E) Future Release (MISIM 3.0): -------------------------- 1) The next release will include a new C-version analog simulator which has been benchmarked to be a factor of 2 to 3 times faster than the current fortran version. 2) The mixed-signal simulator will be enhanced to improve digital cover- age rate (percentage of a mixed A/D circuit which can be processed by the analytic digital macromodel) for better simulation performance. 51: Nelsis Cad Framework (from their 'README' file) Release 4.3 is the latest version of the Nelsis IC Design System. It contains a CAD framework that puts a substantial added-value under the fingertips of the designer by organizing the design information and keeping track of the design evolution. It permits integration of tools of different origin and achieves run-time efficiency. The framework is based on intelligent management of meta data on top of the actual design descriptions; it administers high level information about the design activities and the structure and status of the design, rather than operating at the level of the detailed design descriptions. The framework services, such as flow management, version manage- ment, concurrency control and state management, have been implemented on top of the meta data management module. The framework controls access to the design objects and administers meta data by performing OTO-D queries. Tools operate on top of the framework via the Data Management Interface, obtaining access to the design data according to a nested transaction schema. The Nelsis CAD Framework is available, together with a set of design tools for demonstration purposes, through anonymous ftp from <URL:ftp://dutente.et.tudelft.nl/pub/nelsis> . Release 4.6.1 is now available. More information on NELSIS can be found on WWW at <URL:http://www.ddtc.dimes.tudelft.nl/docs-4.6/docs.html> 52: APLAC, a general purpose circuit simulation and design tool (from Sakari Aaltonen <sakari@picea.hut.fi>) ----------------------------------------- APLAC 6.2 ----------------------------------------- General information APLAC, a program for circuit simulation and analysis, is a joint develop- ment of the Circuit Theory Lab of Helsinki University of Technology and Nokia Corporation's Research Center. The main analysis modes are DC, AC, noise, transient, oscillator, and (multitone harmonic) steady state. APLAC can also be used for measurements with IEEE-488 apparatus. APLAC's transient analysis uses convolution for correct treatment of components with frequency-dependent characteristics. Monte Carlo analysis is avail- able in all basic analysis modes, as is sensitivity analysis in DC and AC modes. N-port Z, Y, and S parameters, as well as two-port H parameters, can be used in AC analysis. APLAC also includes a versatile collection of system level blocks for the simulation and design of analog and digital communication systems. Component models Too many to be listed here. In addition to familiar Spice models, a great number of microwave components (microstrip/stripline) are included. Sys- tem models include formula-based and discrete-time models useful in RF design. The model parameters of the components may have any functional dependency on frequency, time, temperature, or any other parameter. Users can create new components by defining their - possibly nonlinear - static and dynamic characteristics in APLAC's interpreter-type language. Spice- syntax models can be imported. Input APLAC reads its input - the nodes, branches, and model parameters of the components - from a text file. Model libraries can be created and included. Expressions are written in a program-like manner; user func- tions may be defined. Conditional and looping control structures are sup- ported. Output The output results from one or several sweeps of any user-defined func- tion of the circuit parameters, time, frequency, or temperature. The results may be printed or plotted in rectangular or polar coordinates, or on the Smith chart. Graphics output can be directed to an HPGL- or CSDF- type file, or to a graphics file for later viewing. Optimization APLAC includes several optimization methods: gradient, conjugate gra- dient, minmax, random, simulated annealing, tuning (manual optimization) and gravity center (design centering). Any parameter in a design problem can be used as a variable and any user-defined function may act as an objective. Machine environment